The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to circuits, methods and structure for gated lateral bipolar transistors.
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits require the use of an ever increasing number of linked transistors. As the number of transistors required increases, the surface space on silicon chip/die dwindles. It is one objective, then, to construct transistors which occupy less surface area on the silicon chip/die.
Metal-oxide semiconductor field effect transistors (MOS transistors) are prevalent in integrated circuit technology because they generally demand less power than their counterpart, bipolar transistors. Bipolar transistors, on the other hand, also possess certain advantages over MOS transistors, such as speed. Therefore, it is another objective and attempts have been made to combine the technological designs of bipolars and MOS transistors in an effort to maximize the benefits of both transistor types.
Various types of lateral transistors have been historically described and utilized in complementary metal-oxide semiconductor (CMOS) technology. Lateral bipolar transistors have received renewed interest with the advent of bipolar complementary metal-oxide semiconductor (BiCMOS) technologies. Recently the action of newer devices has been described in new terms and a more careful distinction made between the different types of transistor action possible. Both gate-body connected MOS transistors and gated lateral bipolar transistors have been described. The term gate-body connected transistors is used to describe vertical or other device structures where the body of the MOS transistor also serves as the base of a bipolar transistor but each device functions separately as a normal transistor and MOS transistor action is dominant. Applying the gate voltage to the body serves primarily to change the threshold voltage of the MOS transistor.
Other structures are possible where the gate and base are common and the bipolar transistor and MOS transistor are in parallel but the bipolar transistor current is dominant. In a gated lateral transistor, not only the structures but also the operation is merged and most current flows along a surface under the gate in either MOS or bipolar operation. In the case of a gated lateral bipolar transistor, at low gate voltages around threshold (Vt), they can act as gate-body connected MOS transistors. At higher input voltages, Vt or more, the bipolar action can dominate and they are more appropriately described as gated lateral bipolar transistors.
Much effort has been placed into the study of these merged transistor structures. Both vertical and lateral structures have been studied. These studies do not look to solutions for conserving precious die space in the fabrication of integrated circuits. Likewise, previous efforts have not been able to combine low power operation with enhanced operation characteristics and simultaneously maximize switching speeds. It is desirable then to improved transistor structures, circuits and methods which have advanced operation characteristics and low power consumption. Any improved configuration of transistor structure should remain fully integrateable with prevalent integrated circuit design.
The above mentioned problems with integrated circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A structure and method are described which accord these benefits.
In particular, an illustrative embodiment of the present invention includes a gated lateral bipolar transistor. The gated lateral bipolar transistor includes a single crystalline semiconductor structure which has an upper surface and opposing sidewall surfaces. The single crystalline semiconductor structure has a source/emitter region, a body/base region, and a collector/drain region. The source/emitter region and the collector/drain region are located on a first one of the opposing sidewall surfaces. A dielectric layer is disposed between the source/emitter region and the collector/drain region. A gate is formed on the dielectric layer on the first one of the opposing sidewall surfaces. A body contact is coupled to the body/base region on a second one of the opposing sidewall surfaces, such that the transistor exhibits both bipolar junction transistor (BJT) and metal-oxide semiconductor (MOS) action.
In another embodiment, a gated lateral bipolar transistor is provided. The gated lateral bipolar transistor includes a single crystalline semiconductor structure which has an upper surface and opposing sidewall surfaces. The single crystalline semiconductor structure has a source/emitter region, a body/base region, and a collector/drain region. The source/emitter region and the collector/drain region are located on a first one of the opposing sidewall surfaces. A pair of conductive sidewall members are disposed adjacent to the opposing sidewall members and a first one of the pair is separated from a first one of the opposing sidewall surfaces by a gate oxide. The second one of the pair couples directly to a second one of the opposing sidewall surfaces.
In another embodiment, a method of fabricating a gated lateral bipolar transistor is provided. The method includes forming a single crystalline semiconductor structure on a substrate. The structure is formed to include a body/base region, an upper surface, and opposing sidewall surfaces. The method includes forming an insulator layer between the substrate and the single crystalline semiconductor structure. A source/emitter region and a collector/drain region are formed on a first one of the opposing sidewall surfaces. A dielectric layer is formed between the source/emitter region and the collector/drain region. A gate is formed on the dielectric layer and a body contact is coupled to the body/base region on a second one of the opposing sidewall surfaces, such that the transistor exhibits both bipolar junction transistors (BJT) and metal-oxide semiconductor (MOS) action.
In another embodiment, a method of fabricating a gated lateral bipolar transistor is provided. The method includes forming a single crystalline semiconductor structure. The structure is formed to include a body/base region, an upper surface and opposing sidewall surfaces. A source/emitter region and a collector/drain region are formed on a first one of the opposing sidewall surfaces. The method includes forming a pair of conductive sidewall members so that the members are disposed adjacent to the opposing sidewall members. Forming the pair includes forming a gate oxide located between a first one of the pair and the first one of the opposing sidewall surfaces. A second one of the pair is formed coupling directly to a second one of the opposing sidewall surfaces.
Thus, improved transistor structures are provided along with the methods for producing the same. The transistors combine BJT and MOS transistor conduction. These new transistor structures allow for low voltage level operation and enhanced switching action over conventional bipolar complementary metal-oxide semiconductor (BiCMOS) devices. These gated lateral bipolar transistors are fully compatible with CMOS technology. Thus, the transistor structures do not require additional chip surface space, nor additional processing steps.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.